Technical Field
The present invention relates to semiconductor devices and processes, and more particularly to semiconductor devices that employ deposition and exfoliation of layers to form source and drain regions for transistor devices.
Description of the Related Art
Field effect transistors (FETs) often include doped source and drain regions made of a similar material. In one common structure, III-V FETs include source/drain (S/D) regions formed from doped InGaAs (e.g., n+InGaAs). The formation process for forming S/D regions usually requires patterned implantation of n+dopants, which adds time and expense to the process, and may result in junction damage. To avoid ion-implantation, selective epitaxial growth processes may be employed.
The selective epitaxial growth processes for FET structures often form a gate structure (with dielectric sidewall spacers on sides of a gate conductor material) over a substrate, recess regions adjacent to the gate structure and perform a selective epitaxy process to form source and drain (S/D) regions within the recess regions. The S/D regions are doped using a doped layer that is deposited over the gate structure. Dopants from the doped layer are diffused into the S/D regions. Then, a chemical-mechanical polish (CMP) is performed to remove the doped layer from a top of the gate structure. This procedure avoids ion-implantation for doping but requires many additional steps. Selective epitaxial growth limits the process flow and may be expensive and time consuming. Extra CMP steps also add additional time delays and run the risk of damage or other issues to the already formed components on the device.